1. Field of the Invention
The present invention generally relates to high performance field effect transistors suitable for extremely high density semiconductor integrated circuits and, more particularly, to dual gate field effect transistors having the source and drain located one above the other and other semiconductor devices having borderless contacts.
2. Description of the Prior Art
Field effect transistors have been known for a number of years and are now the transistor of choice for use in complex integrated digital circuit for all but the most stringent of high frequency requirements. In general, field effect transistors can be fabricated somewhat more simply and with larger process windows than bipolar transistors and, additionally, allow simplified circuit and device design.
As demands for higher digital switching performance have increased, as well as demands for increased functionality and economy of manufacture, constraints on transistor footprint size (and, hence, current-carrying capacity) have also increased. Further, to reduce power dissipation requirements as more transistors are placed within a given chip space and switching and/or clock frequencies are increased, operation at decreased voltages has been required. Operation at reduced voltage tends to reduce operating margins and the difference in resistance between the on and off states of the transistor. This effect is due to the reduced ability to control depletion at greater distances from the gate dielectric within the conduction channel with reduced voltages.
Therefore, there has been recent interest in field effect transistor designs which include gate electrodes on opposite sides of or fully or partially surrounding the conduction channel. Further, from the standpoints of both performance and circuit design and functionality, it has been found to be very desirable to provide for different voltages to be applied to separated gate structures on opposite sides of the conduction channel.
However, providing one or more gate structures on opposing surfaces of the conduction channel or even a single gate structure extending on different sides of the conduction channel implies increased structural complexity of the transistor. This increased complexity cannot always be achieved at sizes the same as or smaller than conventional field effect transistors. For example, several successful designs have been recently achieved using a vertical fin as a conduction channel with gate structures disposed on the lateral sides thereof. However, the conduction path is substantially parallel to the chip surface and, while the designs allow some structures to be formed at sub-lithographic sizes (e.g. smaller than the resolution of the lithography tool used for resist patterning exposures to form other structures), the source and drain must be physically separated from the gate structure; increasing at least one dimension of the transistor footprint.
Additionally, some lithographic techniques to increase resolution of radiant energy lithography tools, such as phase-shift masks, can only form features of closed geometric shape. This limitation often requires an additional “trimming” process to establish, for example, channel length of transistors and generally compromises the ability to maintain tight control thereof.
Furthers due to the basic nature of lithography and semiconductor processes, it has been an almost universal practice to configure field effect transistors such that the conduction channel extends substantially parallel to the chip surface. While field effect transistors could, in theory, be configured to have the conduction channel extend substantially perpendicular to the chip surface (e.g. “vertically”), as a practical matter, at least the formation of connections to the source, drain and gate of the transistor are made much more difficult in designs proposed to date; reducing manufacturing yield and consuming substantial chip space as well as greatly increasing process complexity.